This repository contains behavioral code for Serial Adder.The following individual components have been modeled and have been providedwith their corresponding test benches:
Implementation of 4- bit serial adder; Implementation of universal shift register; Implementation of Sequential. Verilog code for Full adder using half adder.
- Parrallel Input Serial Output Shift register (PISO) (
piso.v
) - D Flip Flop (
d_flipflop.v
) - Full Adder (
full_adder.v
)
![Serial Serial](/uploads/1/2/6/5/126506164/460514516.png)
File
serial_adder.v
is the master node, the corresponding testbench isserial_adder_tb.v
. To compile and visualise the waveforms (using iverilogand gtkwave), follow these steps:- Install
iverilog
andgtkwave
using the instructions given here. - Clone this repository using the command
git clone https://github.com/RJ722/serial-adder-verilog
. cd serial-adder-verilog
iverilog -o serial_adder.out serial_adder_tb.v
./serial_adder.out
gtkwave serial_adder_tb.vcd # Visualise waveforms
For changing the input values to the adder, please make changes in
serial_adder_tb.v
.